1. Field
This invention relates to control of memory devices, and in particular, control of inputs to memory devices.
2. Description of the Related Art
Random access memory (“RAM”) allows a memory circuit to execute both read and write operations on memory cells. DRAM is a specific category of RAM containing an array of individual memory cells, where each cell includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor. This charge on the storage capacitors may naturally decay over time, even if the capacitors remain electrically isolated. Thus, DRAM cells require periodic refreshing. Refresh commands may be issued explicitly to the DRAM-based device from another device such as a memory controller. Alternatively, during idle periods, where data is not being read from or written to the DRAM device, the device continuously refreshes without receiving external commands. This process is called “self-refresh.” During self-refresh, voltage generators internal to the memory device alternate powering on and powering off to reduce power consumption.
Sometimes a DRAM device will receive a command to exit self-refresh during the power-off phase of the refresh cycle. Because the device is in the power-off state, one or more voltage generators must power on to allow a command decoder to begin executing commands. However, the generators may not reach full power until long after the exit command is received. During this power recovery time, external inputs to the command decoder are unstable. The command decoder may therefore receive and decode a command in error which potentially overwrites or otherwise corrupts portions of data stored in memory.